`timescale 1ns/1ps
module mips_tb();

reg clk, rst;

MIPS_top i_mips_top(
    .clk(clk), .rst(rst)
);

initial
begin
  clk =0;
  forever
  #(20) clk = ~clk;
end

initial
begin
    rst = 1;
    #30
    rst = 0;
    #60
    rst = 1;

    #200000000 $stop;
end
endmodule